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K4S643233F-S(D)E/N/I/P
CMOS SDRAM
2Mx32 Mobile SDRAM 90FBGA
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Revision 1.5 December 2002
Rev. 1.5 Dec. 2002
K4S643233F-S(D)E/N/I/P
512K x 32Bit x 4 Banks SDRAM
FEATURES
* * * * 3.0V & 3.3 power supply. LVCMOS compatible with multiplexed address. Four banks operation. MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). All inputs are sampled at the positive going edge of the system clock . Burst read single-bit write operation. DQM for masking. Auto & self refresh. 64ms refresh period (4K cycle). Extended temperature operation (-25C to 85 C). Industrial temperature operation ( -40C to 85C). 90balls FBGA(-SXXX -Pb, -DXXX -Pb Free).
CMOS SDRAM
GENERAL DESCRIPTION
The K4S643233F is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
* * * * * * *
ORDERING INFORMATION
Part No. K4S643233F-SE/N/I/P75 K4S643233FSE/N/I/P1H K4S643233F-SE/N/I/P1L K4S643233F-DE/N/I/P75 K4S643233F-DE/N/I/P1H K4S643233F-DE/N/I/P1L Max Freq. 133MHz(CL=3) 105MHz(CL=2) 105MHz(CL=2) 105MHz(CL=3)*1 133MHz(CL=3) 105MHz(CL=2) 105MHz(CL=2) 105MHz(CL=3)*1 LVCMOS 90FBGA Pb Free Interface Package 90FBGA Pb
FUNCTIONAL BLOCK DIAGRAM
-S(D)E/N ; Normal/Low Power, Temp : -25 C ~ 85 C. -S(D)I/P ; Normal/Low Power, Temp : -40C ~ 85 C. Note : 1. In case of 40MHz Frequency, CL1 can be supported.
I/O Control
LWE
Data Input Register
LDQM
Bank Select 512K x 32 512K x 32 512K x 32 512K x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
*Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.5 Dec. 2002
K4S643233F-S(D)E/N/I/P
90-Ball FBGA Package Dimension and Pin Configuration
< Bottom View*1 >
E1 9 A e B C D D E F G D1 H J K D/2 L M N P R E E/2 8 7 6 5 4 3 2 1
CMOS SDRAM
< Top View*2 >
90Ball(6x15) CSP 1 A B C D E F G H J K L M N P R DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 7 VD D VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS VD D DQ6 DQ1 VDDQ VD D 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS WE DQ7 DQ5 DQ3 VSSQ DQ0 9 DQ21 DQ19 VDDQ VDDQ VSSQ VD D A1 NC RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2
*2: Top View
Pin Name CLK CS CKE
A A1
Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground [Unit:mm]
A0 ~ A10 BA0 ~ BA1 RAS CAS WE DQM0 ~ DQM3 DQ 0 ~ 31 VDD /VSS VDDQ/VSSQ
Substrate(4Layer)
b
z
*1: Bottom View < Top View*2 >
#A1 Ball Origin Indicator
K4S643233F-XXXX
SAMSUNG
Week
Symbol A A1 E E1 D D1 e b z
Min 0.30 0.40 -
Typ 1.30 0.35 11.00 6.40 13.00 11.20 0.80 0.45 -
Max 1.40 0.40 0.50 0.10
Rev. 1.5 Dec. 2002
K4S643233F-S(D)E/N/I/P
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on V D D supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD , VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
CMOS SDRAM
Unit V V C W mA
Notes : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 C to 85 C for Extended, -40C to 85C for Industrial) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VD D VDDQ VIH VIL VOH VOL ILI Min 2.7 2.7 2.2 -0.3 2.4 -10 Typ 3.0 3.0 3.0 0 Max 3.6 3.6 VDDQ+0.3 0.5 0.4 10 Unit V V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.3V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
Clock
(VDD = 3.0V & 3.3, TA = 23 C, f = 1MHz, VREF =0.9V 50 mV) Pin Symbol CCLK CIN CADD COUT Min Max 4.0 4.0 4.0 6.0 Unit pF pF pF pF Note
RAS, CAS, WE, CS, CKE, DQM0~ DQM3 Address(A0 ~ A10, BA0 ~ BA1) D Q0 ~ DQ31
Rev. 1.5 Dec. 2002
K4S643233F-S(D)E/N/I/P
DC CHARACTERISTICS
CMOS SDRAM
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25C to 85 C for Extended, -40 C to 85C for Industrial) Parameter Symbol Test Condition -75 Operating Current (One Bank Active) Precharge Standby Current in power-down mode ICC1 Burst length = 1 tRC tR C(min) IO = 0 mA CKE VIL(max), t CC = 10ns 80 Version -1H 75 -1L 75 mA 1 Unit Note
ICC2P
0.5 0.5 11
ICC2 PS CKE & CLK VIL(max), tCC = ICC2N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), t CC = 10ns
mA
Precharge Standby Current in non power-down mode ICC2NS Active Standby Current in power-down mode ICC3P
mA 8 5 5 22 mA
ICC3 PS CKE & CLK VIL(max), tCC = ICC3N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA ,Page burst tRC tRC (min) CKE 0.2V -S(D)E/I -S(D)N/P 95 135
mA
Active Standby Current in non power-down mode (One Bank Active) Operating Current Refresh Current Self Refresh Current
ICC3NS ICC4 ICC5 ICC6
22 75 120 2 0.4 75 120
mA mA mA mA 1 2 3 4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S643233F-S(D)E/I** 4. K4S643233F-S(D)N/P** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Rev. 1.5 Dec. 2002
K4S643233F-S(D)E/N/I/P
AC OPERATING TEST CONDITIONS
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition VDDQ
CMOS SDRAM
(VDD = 2.7V ~ 3.6V, TA = -25 C to 85 C for Extended, -40 C to 85C for Industrial) Value 2.4 / 0.4 0.5 x VDDQ tr/tf = 1/1 0.5 x VDDQ See Fig. 2
Vtt = 0.5 x VDDQ
Unit V V ns V
1200 Output 870 30pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
30pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)
Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Symbol - 75 tRRD (min) tRCD (min) tRP(min) tRAS(min) tRAS(max) tR C(min) tRDL(min) tDAL (min) tCDL(min) tBDL (min) tCCD (min) CAS latency=3 Number of valid output data CAS latency=2 CAS latency=1 65 15 19 19 45 Version -1H 19 19 19 50 100 70 2 tRDL + tRP 1 1 1 2 1 0 ea 5 84 -1L 19 24 24 60 ns ns ns ns us ns CLK CLK CLK CLK 1 2,3 3 2 2 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.5 Dec. 2002
K4S643233F-S(D)E/N/I/P
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=1 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 CAS latency=1 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS latency=3 CLK to output in Hi-Z CAS latency=2 CAS latency=1 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. tSHZ tC H tC L tSS tSH tSLZ tOH 2.5 2.5 2.5 2.5 2.0 1.0 1 5.4 7 tSAC tC C Symbol Min 7.5 9.5 5.4 7 2.5 2.5 3 3 2.5 1.5 1 7 7 1000 - 75 Max Min 9.5 9.5 7 7 2.5 2.5 2.5 3 3 2.5 1.5 1 1000 -1H Max Min 9.5 12 25 -1L
CMOS SDRAM
Unit Max
Note
1000
ns
1
7 8 20 ns 1,2
ns
2
ns ns ns ns ns 7 8 20 ns
3 3 3 3 2
Notes : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Rev. 1.5 Dec. 2002
K4S643233F-S(D)E/N/I/P
SIMPLIFIED TRUTH TABLE(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
CMOS SDRAM
A10 /AP
A9 ~ A 0
Note
H H
X H L H X X
L L L H L L
L L H X L H
L L H X H L
L H H X H H
X X
OP CODE X
1, 2 3 3 3 3
L H H
X X X V V
X Row Address L H L
Column Address (A0~ A7) Column Address (A0~ A7)
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Clock Suspend or Active Power Down Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
H X
V X
L H
X
H L H
L H L
X X X
X
X X V X X 7
L H H
H
X
H L
X H
X H
X H
X
Notes : 1. OP Code : Operand Code A0 ~ A 10 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev. 1.5 Dec. 2002

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